Panel stacking of BGA devices to form three-dimensional modules

ABSTRACT

A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] (Not Applicable)

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

[0002] (Not Applicable)

BACKGROUND OF THE INVENTION

[0003] The present invention relates generally to chip stacks, and moreparticularly to a chip stack having connections routed from the bottomto the perimeter thereof to allow multiple integrated circuit chips suchas BGA devices to be quickly, easily and inexpensively verticallyinterconnected in a volumetrically efficient manner.

[0004] Multiple techniques are currently employed in the prior art toincrease memory capacity on a printed circuit board. Such techniquesinclude the use of larger memory chips, if available, and increasing thesize of the circuit board for purposes of allowing the same toaccommodate more memory devices or chips. In another technique, verticalplug-in boards are used to increase the height of the circuit board toallow the same to accommodate additional memory devices or chips.

[0005] Perhaps one of the most commonly used techniques to increasememory capacity is the stacking of memory devices into a vertical chipstack, sometimes referred to as 3D packaging or Z-Stacking. In theZ-Stacking process, from two (2) to as many as eight (8) memory devicesor other integrated circuit (IC) chips are interconnected in a singlecomponent (i.e., chip stack) which is mountable to the “footprint”typically used for a single package device such as a packaged chip. TheZ-Stacking process has been found to be volumetrically efficient, withpackaged chips in TSOP (thin small outline package) or LCC (leadlesschip carrier) form generally being considered to be the easiest to usein relation thereto. Though bare dies or chips may also be used in theZ-Stacking process, such use tends to make the stacking process morecomplex and not well suited to automation.

[0006] In the Z-Stacking process, the IC chips or packaged chips must,in addition to being formed into a stack, be electrically interconnectedto each other in a desired manner. There is known in the prior artvarious different arrangements and techniques for electricallyinterconnecting the IC chips or packaged chips within a stack. Examplesof such arrangements and techniques are disclosed in Applicant's U.S.Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep.11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OFMAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitledMODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.

[0007] The various arrangements and techniques described in these issuedpatents and other currently pending patent applications of Applicanthave been found to provide chip stacks which are relatively easy andinexpensive to manufacture, and are well suited for use in a multitudeof differing applications. The present invention provides yet a furtheralternative arrangement and technique for forming a volumetricallyefficient chip stack. In the chip stack of the present invention,connections are routed from the bottom of the chip stack to theperimeter thereof so that interconnections can be made vertically whichallows multiple integrated circuit chips such as BGA, CSP, fine pitchBGA, or flip chip devices to be stacked in a manner providing thepotential for significant increases in the production rate of the chipstack and resultant reductions in the cost thereof.

BRIEF SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, there is provided achip stack comprising at least two base layers (i.e., an upper baselayer and a lower base layer). Each of the base layers includes a basesubstrate having a first conductive pattern disposed thereon. The chipstack further comprises at least one interconnect frame having a secondconductive pattern disposed thereon. The interconnect frame is disposedbetween the upper and lower base layers, with the second conductivepattern being electrically connected to the first conductive pattern ofeach of the base layers. In addition to the base layers and interconnectframe, the chip stack comprises at least two integrated circuit chipswhich are electrically connected to respective ones of the firstconductive patterns. The integrated circuit chip electrically connectedto the first conductive pattern of the lower base layer is at leastpartially circumvented by the interconnect frame and at least partiallycovered by the upper base layer. The chip stack further preferablycomprises a transposer layer which includes a transposer substratehaving a third conductive pattern disposed thereon. The first conductivepattern of the lower base layer is electrically connected to the thirdconductive pattern of the transposer layer.

[0009] In the present chip stack, the base substrate of each of the baselayers defines opposed, generally planar top and bottom surfaces. Thefirst conductive pattern itself comprises first and second sets of basepads which are disposed on the top surface of the base substrate, withthe base pads of the second set being electrically connected torespective ones of the base pads of the first set via conductive traces.In addition to the first and second sets of base pads, the firstconductive pattern includes a third set of base pads disposed on thebottom surface of the base substrate and electrically connected torespective ones of the base pads of the second set. More particularly,each of the base pads of the second set is preferably electricallyconnected to a respective one of the base pads of the third set via abase feed-through hole. The base feed-through hole is preferably pluggedwith a conductive material selected from the group consisting of nickel,gold, tin, silver epoxy, and combinations thereof. The integratedcircuit chips are disposed upon respective ones of the top surfaces ofthe base substrates and electrically connected to at least some of thebase pads of respective ones of the first sets. Additionally, the basepads of the second set of the lower base layer are electricallyconnected to the second conductive pattern of the interconnect frame, asare the base pads of the third set of the upper base layer.

[0010] The interconnect frame of the chip stack itself defines opposed,generally planar top and bottom surfaces, with the second conductivepattern comprising first and second sets of frame pads disposed onrespective ones of the top and bottom surfaces. Each of the frame padsof the first set is electrically connected to a respective one of theframe pads of the second set via a frame feed-through hole which is alsoplugged with a conductive material preferably selected from the groupconsisting of nickel, gold, tin, silver epoxy, and combinations thereof.The interconnect frame is preferably disposed between the upper andlower base layers such that the frame pads of the second set areelectrically connected to respective ones of the base pads of the secondset of the lower base layer, with the frame pads of the first set beingelectrically connected to respective ones of the base pads of the thirdset of the upper base layer.

[0011] The transposer substrate of the present chip stack also definesopposed, generally planar top and bottom surfaces, with the thirdconductive pattern comprising first and second sets of transposer padsdisposed on respective ones of the top and bottom surface of thetransposer substrate. The transposer pads of the first set areelectrically connected to respective ones of the transposer pads of thesecond set. Additionally, the base pads of the third set of the lowerbase layer are electrically connected to respective ones of thetransposer pads of the first set.

[0012] In the present chip stack, the transposer pads of the first set,the frame pads of the first and second sets, and the base pads of thesecond and third sets are preferably arranged identical patterns.Additionally, the transposer and base substrates each preferably have agenerally rectangular configuration defining opposed pairs oflongitudinal and lateral peripheral edge segments. The interconnectframe itself preferably has a generally rectangular configurationdefining opposed pairs of longitudinal and lateral side sections. Thetransposer pads of the first set extend along the longitudinal andlateral peripheral edge segments of the transposer substrate. Similarly,the first and second sets of frame pads extend along the longitudinaland lateral side sections of the interconnect frame, with the second andthird sets of base pads extending along the longitudinal and lateralperipheral edge segments of the base substrate. Each of the transposerpads of the second set preferably has a generally sphericalconfiguration, with each of the transposer pads of the first set andeach of the frame pads of the first and second sets preferably having agenerally semi-spherical configuration.

[0013] Each of the integrated circuit chips of the present chip stackpreferably comprises a body having opposed, generally planar top andbottom surfaces, and a plurality of conductive contacts disposed on thebottom surface of the body. The conductive contacts of each of theintegrated circuit chips are electrically connected to respective onesof the base pads of the first set of a respective one of the firstconductive patterns. The transposer pads of the second set, the basepads of the first set, and the conductive contacts are themselvespreferably arranged in identical patterns. The chip stack furtherpreferably comprises a layer of flux/underfill (also referred to as a“no flow-fluxing underfill”) disposed between the bottom surface of thebody of each of the integrated circuit chips and respective ones of thetop surfaces of the base substrates. Each layer of flux/underfill ispreferably spread over the base pads of the first set of a respectiveone of the first conductive patterns. The body of each of the integratedcircuit chips and the interconnect frame are preferably sized relativeto each other such that the top surface of the body of the integratedcircuit chip electrically connected to the lower base panel and at leastpartially circumvented by the interconnect frame does not protrudebeyond the top surface thereof. The integrated circuit chips arepreferably selected from the group consisting of a BGA device, a finepitch BGA device, a CSP device, and a flip chip device. Further, thetransposer and base substrates are each preferably fabricated from apolyamide or other suitable circuit board material which may be as thinas about 0.010 inches.

[0014] Those of ordinary skill in the art will recognize that a chipstack of the present invention may be assembled to include more than twobase layers, more than one interconnect frame, and more than twointegrated circuit chips. In this respect, a multiplicity of additionalinterconnect frames, base layers, and integrated circuit chips may beincluded in the chip stack, with the second conductive pattern of eachof the interconnect frames being electrically connected to the firstconductive patterns of any adjacent pair of base layers, and each of theintegrated circuit chips being electrically connected to the firstconductive pattern of a respective one of the base layers.

[0015] Further in accordance with the present invention, there isprovided a method of assembling a chip stack. The method comprises theinitial step of electrically connecting an integrated circuit chip to afirst conductive pattern of a base layer. Thereafter, a secondconductive pattern of an interconnect frame is electrically connected tothe first conductive pattern such that the interconnect frame at leastpartially circumvents the integrated circuit chip. Another integratedcircuit chip is then electrically connected to the first conductivepattern of another base layer. The first conductive pattern of one ofthe base layers is then electrically connected to the second conductivepattern of the interconnect frame such that one of the integratedcircuit chips is disposed between the base layers. The method mayfurther comprise the step of electrically connecting the firstconductive pattern of one of the base layers to a third conductivepattern of a transposer layer. In the present assembly method, a layerof flux/underfill is preferably applied to (i.e., spread over) each ofthe base layers over portions of the first conductive patterns prior tothe electrical connection of respective ones of the integrated circuitchips thereto. All of the electrical connections in the present assemblymethod are preferably accomplished via soldering.

[0016] Still further in accordance with the present invention, there isprovided a method of assembling a chip stack which comprises the initialsteps of providing a transposer panel, at least two base panels, and atleast one frame panel which each have opposed surfaces and a pluralityof conductive pads disposed on the opposed surfaces thereof. A pluralityof integrated circuit chips are also provided which each have opposedsides and include conductive contacts disposed on one of the sidesthereof. In this assembly method, integrated circuit chips are placedupon each of the base panels such that the conductive contacts of eachof the integrated circuit chips are disposed on at least some of theconductive pads of respective ones of the base panels. Thereafter, oneof the base panels is stacked upon the transposer panel such that atleast some of the conductive pads of the base panel are disposed on atleast some of the conductive pads of the transposer panel. The framepanel is then stacked upon the base panel such that at least some of theconductive pads of the frame panel are disposed on at least some of theconductive pads of the base panel. Another base panel is then stackedupon the frame panel such that at least some of the conductive pads ofthe base panel are disposed on at least some of the conductive of theframe panel.

[0017] The assembly method further comprises bonding the conductivecontacts of the integrated circuit chips to at least some of theconductive pads of the base panel upon which the integrated circuitchips are positioned, bonding at least some of the conductive pads ofone of the base panels to at least some of the conductive pads of thetransposer panel, and bonding at least some of the conductive pads ofthe frame panel to at least some of the conductive pads of each of thebase panels. The assembly method may further comprise the steps ofstacking spacer sheets between one of the base panels and the transposerpanel, and between the frame panel and each of the base panels. Thespacer sheets each have opposed surfaces and a plurality of openingsdisposed therein. When stacked between the base and transposer panelsand between the frame and base panels, the openings of the spacer sheetsare aligned with the conductive pads of such panels.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] These, as well as other features of the present invention, willbecome more apparent upon reference to the drawings wherein:

[0019]FIG. 1 is a top perspective view of a chip stack constructed inaccordance with the present invention;

[0020]FIG. 2 is an exploded view of the chip stack shown in FIG. 1;

[0021]FIG. 3 is an exploded view of the various components which arestacked upon each other in accordance with a preferred method ofassembling the chip stack of the present invention;

[0022]FIG. 4 is a partial cross-sectional view of the components shownin FIG. 3 as stacked upon each other prior to a solder reflow step ofthe present assembly method;

[0023]FIG. 4a is an enlargement of the encircled region 4 a shown inFIG. 4;

[0024]FIG. 5 is partial cross-sectional view similar to FIG. 4illustrating the components shown in FIG. 3 as stacked upon each othersubsequent to the completion of the solder reflow step of the presentassembly method; and

[0025]FIG. 5a is an enlargement of the encircled region 5 a shown inFIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

[0026] Referring now to the drawings wherein the showings are forpurposes of illustrating a preferred embodiment of the present inventiononly, and not for purposes of limiting the same, FIG. 1 perspectivelyillustrates a chip stack 10 assembled in accordance with the presentinvention. The chip stack 10 comprises at least two identicallyconfigured base layers 12. Each of the base layers 12 itself comprises arectangularly configured base substrate 14 which defines a generallyplanar top surface 16, a generally planar bottom surface 18, an opposedpair of longitudinal peripheral edge segments 20, and an opposed pair oflateral peripheral edge segments 22.

[0027] Disposed on the base substrate 14 of each base layer 12 is afirst conductive pattern which itself preferably comprises a first setof base pads 24 and a second set-of base pads 26 which are each disposedon the top surface 16 of the base substrate 14. The base pads 24 of thefirst set are preferably arranged in a generally rectangular pattern orarray in the central portion of the base substrate 14, with the basepads 26 of the second set extending linearly along the longitudinal andlateral peripheral edge segments 20, 22 of the base substrate 14. Thebase pads 24 of the first set are electrically connected to respectiveones of the base pads 26 of the second set via conductive traces 28. Inaddition to the base pads 24, 26 of the first and second sets, the firstconductive pattern of each base layer 12 comprises a third set of basepads 30 which is disposed on the bottom surface 18 of the base substrate14. The base pads 30 of the third set are preferably arranged in anidentical pattern to the base pads 26 of the second set, and extendlinearly along the longitudinal and lateral peripheral edge segments 20,22 of the base substrate 14 such that each of the base pads 30 of thethird set is aligned with and electrically connected to a respective oneof the base pads 26 of the second set.

[0028] As is best seen in FIGS. 3-5, each of the base pads 26 of thesecond set is electrically connected to a respective one of the basepads 30 of the third set via a base feed-through hole 32. Each basefeed-through hole 32 is preferably plugged with a conductive material.The conductive material is preferably selected from the group consistingof nickel, gold, tin, silver epoxy, and combinations thereof. The basepads 26, 30 of the second and third sets, as well as the base pads 24 ofthe first set, each preferably have a generally circular configuration.In this respect, each base feed-through hole 32 preferably extendsaxially between each corresponding, coaxially aligned pair of the basepads 26, 30 of the second and third sets. The base pads 26, 30 of thesecond and third sets are preferably formed upon (i.e., surface platedto) the base substrate 14 subsequent to the plugging of the basefeed-through holes 32 and are used to cover the opposed, open endsthereof. If the base feedthrough holes 32 were left unplugged, soldercoming into contact with the base pads 26, 30 of the second and thirdsets would tend to wick into the base feed-through holes 32 upon thereflow of the solder (which will be discussed below), thus robbing thebase pads 26, 30 of solder needed to facilitate various electricalconnections in the chip stack 10.

[0029] In addition to the base layers 12, the chip stack 10 of thepresent invention comprises at least one rectangularly configuredinterconnect frame 34. The interconnect frame 34 defines a generallyplanar top surface 36, a generally planar bottom surface 38, an opposedpair of longitudinal side sections 40, and an opposed pair of lateralside sections 42. Disposed on the interconnect frame 34 is a secondconductive pattern which itself preferably comprises a first set offrame pads 44 disposed on the top surface 36, and a second set of framepads 46 disposed on the bottom surface 38. The frame pads 44, 46 of thefirst and second sets are preferably arranged in patterns which areidentical to each other, and to the patterns of the second and thirdsets of base pads 26, 30 of each of the base layers 12. In this respect,the frame pads 44, 46 of the first and second sets each extend linearlyalong the longitudinal and lateral side sections 40, 42 of theinterconnect frame 34, with each of the frame pads 44 of the first setbeing aligned with and electrically connected to a respective one of theframe pads 46 of the second set. As best seen in FIGS. 4(a) and 5(a),similar to the electrical connection of the base pads 26, 30 of thesecond and third sets to each other, the electrical connection of eachof the frame pads 44 of the first set to a respective one of the framepads 46 of the second set is preferably accomplished via a framefeedthrough hole 48 which is also preferably plugged with a conductivematerial. The conductive material is preferably selected from the samegroup used as the conductive material to plug the base feed-throughholes 32, i.e., nickel, gold, tin, silver epoxy, and combinationsthereof. Each of the frame feed-through holes 48 preferably extendsaxially between a corresponding, coaxially aligned pair of the framepads 44, 46 of the first and second sets, with the plugging of the framefeed-through holes 48 preferably occurring prior to the surface platingof the frame pads 44, 46 of the first and second sets to respective onesof the top and bottom surfaces 36, 38 of the interconnect frame 34.

[0030] In the preferred embodiment, the interconnect frame 34 ispreferably prepared for use in the chip stack 10 by forming generallysemi-spherically shaped solder bumps 50 on each of the frame pads 44, 46of the first and second sets. These solder bumps 50 are preferablyformed by first stenciling solder paste onto the frame pads 44, 46 ofthe first and second sets, and thereafter reflowing the solder paste toform the solder bumps 50. The use of a six mil thick stencil with anaperture approximately the same size as each of the frame pads 44, 46will facilitate the formation of a solder bump 50 approximately six milshigh. As indicated above, the frame pads 44, 46 of the first and secondsets are formed (i.e., surface plated) subsequent to the framefeed-through holes 48 being plugged with the conductive material. If theframe feed-through holes 48 were left unplugged, each frame feed-throughhole 48 could trap flux or air which would blow out the solder duringthe reflow cycle used to form the solder bumps 50 on each corresponding,coaxially aligned pair of frame pads 44, 46 of the first and secondsets.

[0031] In the chip stack 10, the interconnect frame 34 is disposedbetween the base layers 12, with the second conductive pattern of theinterconnect frame 34 being electrically connected to the firstconductive pattern of each of the base layers 12. More particularly, theframe pads 46 of the second set are electrically connected to respectiveones of the base pads 26 of the second set of one of the base layers 12(i.e., the base layer 12 immediately below the interconnect frame 34 inthe chip stack 10) , with the frame pads 44 of the first set beingelectrically connected to respective ones of the base pads 30 of thethird set of one of the base layers 12 (i.e., the base layer 12immediately above the interconnect frame 34 in the chip stack 10). Dueto the base pads 26, 30 of the second and third sets and the frame pads44, 46 of the first and second sets all being arranged in identicalpatterns, each coaxially aligned pair of frame pads 44, 46 of the firstand second sets is itself coaxially aligned with a coaxially aligned setof base pads 26, 30 of the second and third sets of each of the adjacentbase layers 12. The electrical connection of the second conductivepattern of the interconnect frame 34 to the first conductive pattern ofeach of the adjacent base layers 12 is preferably facilitated via asoldering process which will be described in more detail below.

[0032] The chip stack 10 of the present invention further preferablycomprises a transposer layer 52. The transposer layer 52 itselfcomprises a rectangularly configured transposer substrate 54 whichdefines a generally planar top surface 56, a generally planar bottomsurface 58, an opposed pair of longitudinal peripheral edge segments 60,and an opposed pair of lateral peripheral edge segments 62. Disposed onthe transposer substrate 54 is a third conductive pattern. The thirdconductive pattern comprises a first set of transposer pads 64 which aredisposed on the top surface 56 of the transposer substrate 54, and asecond set of transposer pads 66 which are disposed on the bottomsurface 58 thereof. The transposer pads 64 of the first set areelectrically connected to respective ones of the transposer pads 66 ofthe second set via conductive traces. The transposer pads 64 of thefirst set are preferably arranged in a pattern which is identical to thepatterns of the second and third sets of base pads 26, 30 and the firstand second sets of frame pads 44, 46. In this respect, the transposerpads 64 of the first set extend linearly along the longitudinal andlateral peripheral edge segments 60, 62 of the transposer substrate 54.The transposer pads 66 of the second set are themselves preferablyarranged in a generally rectangular pattern or array in the centralportion of the bottom surface 58 of the transposer substrate 54, withthe pattern of the transposer pads 66 of the second set preferably beingidentical to the pattern of the base pads 24 of the first set of each ofthe base layers 12.

[0033] In the preferred embodiment, the transposer layer 52 is preparedfor use in the chip stack 10 by forming generally spherically shapedsolder balls 68 on each of the transposer pads 66 of the second set.These solder balls 68 are preferably formed by stencil printing solderpaste onto each of the transposer pads 66 of the second set, andthereafter reflowing the solder paste to form the solder balls 68. Theaperture in the stencil used to form the solder balls 68 is typicallylarger than each of the transposer pads 66 and thick enough to depositsufficient solder to form the solder balls 68. As seen in FIG. 3, thetransposer layer 52 is also prepared for use in the chip stack 10 byforming generally semi-spherically shaped solder bumps 67 on each of thetransposer pads 64 of the first set. These solder bumps 67 arepreferably formed in the same manner previously described in relation tothe formation of the solder bumps 50 on the frame pads 44, 46 of thefirst and second sets.

[0034] In the chip stack 10, the first conductive pattern of one of thebase layers 12 (i.e., the lowermost base layer 12 in the chip stack 10)is electrically connected to the third conductive pattern of thetransposer layer 52. More particularly, each of the base pads 30 of thethird set of the lowermost base, layer 12 is electrically connected to arespective one of the transposer pads 64 of the first set. Due to thebase pads 30 of the third set and the transposer pads 64 of the firstset being arranged in identical patterns, each of the base pads 30 ofthird set is coaxially alignable with a respective one of the transposerpads 64 of the first set, with the electrical connection therebetweenpreferably being facilitated via soldering as will be discussed in moredetail below.

[0035] In the present chip stack 10, the base pads 24, 26, 30 of thefirst, second and third sets, the conductive traces 28, the frame pads44, 46 of the first and second sets, and the transposer pads 64, 66 ofthe first and second sets are each preferably fabricated from very thincopper having a thickness in the range of from about five microns toabout twenty-five microns through the use of conventional etchingtechniques. Advantageously, the use of thin copper for the various padsand traces 28 allows for etching line widths and spacings down to apitch of about 4 mils which substantially increases the routing densityon each of the base layers 12, as well as the transposer layer 52.Additionally, the base substrate 14, the interconnect frame 34, and thetransposer substrate 54 are each preferably fabricated from either FR-4,polyamide, or some other suitable material which can easily be routed.As indicated above, all of the base feed-through holes 32 and framefeed-through holes 48 are plugged with a conductive material prior tothe surface plating procedure used to form the base pads 24, 26, 30 ofthe first, second and third sets, and the frame pads 44, 46 of the firstand second sets. The material used to form each base substrate 14 and/orthe transposer substrate 54 may be as thin as about 0.010 inches or maybe a thicker multilayer structure.

[0036] The chip stack 10 of the present invention further comprises atleast two identically configured integrated circuit chips 70 which areelectrically connected to respective ones of the first conductivepatterns of the base layers 12. Each of the integrated circuit chips 70preferably comprises a rectangularly configured body 72 defining agenerally planar top surface 74, a generally planar bottom surface 76,an opposed pair of longitudinal sides 78, and an opposed pair of lateralsides 80. Disposed on the bottom surface 76 of the body 72 are aplurality of generally spherically shaped conductive contacts 82 whichare preferably arranged in a pattern identical to the patterns of thebase pads 24 of the first set and the transposer pads 66 of the secondset. The conductive contacts 82 of each of the integrated circuit chips70 are electrically connected to respective ones of the base pads 24 ofthe first set of a respective one of the first conductive patterns ofthe base layers 12. Due to the conductive contacts 82 and base pads 24of each of the first sets being arranged in identical patterns, theconductive contacts 82 of each of the integrated circuit chips 70 arecoaxially alignable with respective ones of the base pads 24 of thecorresponding first set. In each of the integrated circuit chips 70,solder is preferably pre-applied to each of the conductive contacts 82thereof. The electrical connection of the conductive contacts 82 of eachintegrated circuit chip 70 to respective ones of the base pads 24 of thefirst set of a respective one of the first conductive patterns ispreferably accomplished via soldering in a manner which will bediscussed in more detail below. Additionally, each of the integratedcircuit chips 70 is preferably a BGA (ball grid array) device, thoughthe same may alternatively comprise either a CSP device or a flip chipdevice.

[0037] In the present chip stack 10, a layer 84 of flux/underfill ispreferably disposed between the bottom surface 76 of the body 72 of eachof the integrated circuit chips 70 and respective ones of the topsurfaces 16 of the base substrates 14. Each layer 84 of theflux/underfill is preferably spread over the base pads 24 of the firstset of a respective one of the first conductive patterns of the baselayers 12. Each layer 84 substantially encapsulates the conductivecontacts 82 of the corresponding integrated circuit chip 70 when thesame is electrically connected to the first conductive pattern of arespective one of the base layers 12.

[0038] Prior to the attachment of the integrated circuit chip 70 to arespective base layer 12, a bakeout cycle is required to drive out themoisture in the base layer 12 and the corresponding integrated circuitchip 70. A cycle of approximately eight hours at about 125° Celsius isdesirable, which is followed by storage in a dry nitrogen atmosphereuntil use. The first step in the attachment of the integrated circuitchip 70 to the corresponding base layer 12 is the precise deposition ofthe layer 84 of an appropriate flux/underfill material over the basepads 24 of the corresponding first set. The integrated circuit chip 70is then placed over the pad area, squeezing out the flux/underfillmaterial of the layer 84 to the longitudinal and lateral sides 78, 80 ofthe body 72 and seating the conductive contacts 82 onto respective onesof the base pads 24 of the corresponding first set. If done properly,the layer 84 of the flux/underfill material, when cured, will have novoids or minimum voids. The base layer 12 having the integrated circuitchip 70 positioned thereupon in the above-described manner is then runthrough a solder reflow cycle with no dwelling time at an intermediatetemperature of approximately 150° Celsius. A post cure cycle to completethe polymerization of the layer 84 of the flux/underfill material may berequired depending on the particular flux/underfill material used in thelayer 84. At this juncture, the base layer 12 having the integratedcircuit chip 70 electrically connected thereto may be electricallytested.

[0039] In the prior art, the standard approach for the attachment orelectrical connection of the conductive contacts of a BGA device to anattachment or pad site is to first flux the pad site or conductivecontacts of the BGA device, place the BGA device on the pad site in theproper orientation, reflow the solder pre-applied to the conductivecontacts of the BGA device to facilitate the electrical connection tothe pad site, clean, then underfill and cure. The cleaning steptypically requires considerable time since the gap under the bottomsurface of the body of the BGA device is very small and very difficultto penetrate with standard cleaning methods. Also, the removal of thecleaning fluid (which is generally water) requires long bakeout times.

[0040] The underfill of an epoxy between the bottom surface of the bodyof the BGA device and the top surface of the substrate having the padsite thereon is a relatively easy procedure, but is very slow. If ano-clean flux is used for attachment, the residue from the fluxtypically becomes entrapped within the epoxy underfill and may causecorrosion problems. A subsequent solder reflow process to facilitate theattachment of the chip stack to a main printed circuit board (PCB) oftencauses the residue flux to vaporize which exerts pressure on the solderjoints and could delaminate the structure. Most underfill materialsbecome very hard (i.e., greater than ninety shore D) and are cured at atemperature of less than about 180° Celsius. The solder is solid at thistemperature and the underfill encases the solder with no room forexpansion. The solder from the conductive contacts of the BGA deviceexpands when molten again, thus exerting pressure which can delaminatethe structure. If the chip stack is not subjected to subsequent reflowtemperatures when completed, there is no problem. However, the chipstack must be able to withstand the subsequent reflow temperature.

[0041] The flux/underfill material used for the layer 84 provides bothflux and underfill properties with one formulation. As the temperaturerises during the solder reflow process which will be discussed below,the flux characteristics of the material aid in the solder process, withextended exposure to the peak solder reflow temperature beginning thepolymerization process of the underfill portion of the material. Theflux is incorporated into the underfill, thus becoming one compatiblematerial which is cured above the melting point of solder. Thus, thereis room within the encased solder for expansion at the reflowtemperature. No cleaning steps are required, though careful dispensingof the correct volume and accurate placement of the integrated circuitchip 70 upon its corresponding base layer 12 is critical.

[0042] The complete chip stack 10 shown in FIG. 1 includes a transposerlayer 52, four base layers 12, three interconnect frames 34, and fourintegrated circuit chips 70. The first conductive pattern of thelowermost base layer 12 is electrically connected to the thirdconductive pattern of the transposer layer 52 in the above-describedmanner. Additionally, each of the interconnect frames 34 is disposed orpositioned between an adjacent pair of base layers 12, with the secondconductive pattern of each of the interconnect frames 34 beingelectrically connected to the first conductive pattern of such adjacentpair of base layers 12 in the above-described manner. Since theconductive contacts 82 of each of the integrated circuit chips 70 areelectrically connected to respective ones of the base pads 24 of thefirst set of respective ones of the first conductive patterns, theintegrated circuit chips 70 other than for the uppermost integratedcircuit chip 70 are disposed between adjacent pairs of the base layers12 and are each circumvented by a respective one of the interconnectframes 34. Thus, the bodies 72 of the integrated circuit chips 70 andthe interconnect frames 34 are preferably sized relative to each othersuch that the top surface 74 of the body 72 of an integrated circuitchip 70 which is circumvented by an interconnect frame 34 does notprotrude beyond the top surface 36 thereof.

[0043] As also indicated above, all the various electrical connectionswithin the chip stack 10 are preferably facilitated via soldering. Thetransposer pads 66 of the second set, which are spherically shaped asindicated above, form a ball grid array on the bottom of the chip stack10 which is specifically suited for facilitating the attachment of thechip stack 10 to a printed circuit board (PCB). Those of ordinary skillin the art will recognize that the chip stack 10 may be assembled toinclude fewer or greater than four base layers 12, three interconnectframes 34, and four integrated circuit chips 70.

[0044] Having thus described the structural attributes of the chip stack10, the preferred method of assembling the same will now be describedwith specific reference to FIGS. 3, 4, 4(a), 5 and 5(a). In accordancewith the present invention, multiple chip stacks 10 may be concurrentlyassembled through the use of a transposer panel 86, at least two basepanels 88, at least one frame panel 90, at least three spacer sheets 92,and a plurality of integrated circuit chips 70. The transposer panel 86is formed to include multiple groups of the first and second sets oftransposer pads 64, 66 with such groups being formed on the transposerpanel 86 in spaced relation to each other. Similarly, each of the basepanels 88 is formed to include multiple groups of the first, second andthird sets of base pads 24, 26, 30, with the frame panels 90 each beingformed to include multiple groups of the first and second sets of framepads 44, 46. As indicated above, the transposer panel 86 is preparedsuch that the transposer pads 64 of the first set of each group have thesolder bumps 67 formed thereon, with the transposer pads 66 of thesecond set of each group having the solder balls 68 formed thereon.Similarly, each of the frame panels 90 is prepared such that the firstand second sets of frame pads 44, 46 of each group have the solder bumps50 formed thereon. The spacer sheets 92 are each formed to define aplurality of rectangularly configured openings 94, the length and widthdimensions of which exceed those of the base and transposer substrates14, 54 and interconnect frames 34 which are substantially equal to eachother.

[0045] In a preferred assembly process, the integrated circuit chips 70are electrically connected to respective ones of each of the first setsof base pads 24 included on each of the base panels 88. Such electricalconnection is accomplished in the above-described manner. Subsequent tothe pre-attachment of the integrated circuit chips 70 to the base panels88, flux/underfill material is dispensed onto each of the solder bumps67 of the transposer panel 86, with the flux/underfill material alsobeing dispensed onto all of the solder bumps 50 of each of the framepanels 90. The transposer panel is then cooperatively engaged to astacking fixture such that the solder balls 68 face or are directeddownwardly. A spacer sheet 92 is then stacked upon the transposer panel86 such that the transposer pads 64 of the first set of each group arealigned with respective ones of the openings 94 within the spacer sheet92. A base panel 88 is then stacked upon the spacer sheet 92 such thatthe base pads 30 of the third set of each group face or are directeddownwardly and are aligned with respective ones of the openings 94 andrespective ones of the transposer pads 64 of the first set of thecorresponding group upon the transposer panel 86 immediately therebelow.Another spacer sheet 92 is then stacked upon the base panel 88 such thatthe base pads 24, 26 of the first and second sets of each group arealigned with respective ones of the openings 94.

[0046] In the next step of the assembly process, a frame panel 90 isstacked upon the uppermost spacer sheet 92 such that the bodies 72 ofthe integrated circuit chips 70 are each circumvented by the frame panel90. Another spacer sheet 92 is then stacked upon the frame panel 90 suchthat the frame pads 44 of the first set of each group are aligned withrespective ones of the openings 94. Another base panel 88 is thenstacked upon the uppermost spacer sheet 92 in a manner wherein the basepads 30 of the third set of each group of such uppermost base panel 88are aligned with respective ones of the openings 94 and respective onesof the frame pads 44 of the first set of the corresponding group uponthe frame panel 90 immediately therebelow. As will be recognized, theabove-described stacking process may be continued or repeated to form achip stack having a greater number of electrically interconnectedintegrated circuit chips 70.

[0047] Upon the stacking of the various panels and sheets in theabove-described manner, a pressure plate is applied to the top of thestack to maintain such panels and sheets in prescribed orientationsrelative to each other. The stacked panels and sheets are then subjectedto heat at a level sufficient to facilitate the reflow of the solderbumps 50, 67. The solder reflow cycle is typically conducted in atemperature range of from about 215° Celsius to about 250° Celsius. Uponthe completion of solder reflow process, the individual chip stacks areseparated through the use of a router.

[0048] In the preferred assembly method as discussed above, the spacersheets 92 are needed only for the solder reflow process, and do notbecome part of each resultant chip stack formed by the completion of therouting process. The solder bumps 50, 67 are slightly higher than eachspacer sheet 92. Since light pressure is applied to the various panelsand sheets during the solder reflow process, the solder bumps 50, 67collapse, thus making the appropriate electrical connections to thecorresponding pads (i.e., the base pads 26, 30 of either the second orthird sets). Thus, the spacer sheets 92 keep the solder from beingsqueezed out and bridging to neighboring pads. A spacing of from aboutfour mils to about six mils can be accomplished using spacer sheets 92which are fabricated from paper. The paper can be easily punched to formthe openings 94, does not interfere with the routing process, canwithstand the solder reflow temperature in the aforementioned range, andis inexpensive. The paper spacer sheets 92 would be sized the same asthe transposer, base and frame panels 86, 88, 90, and punched to includeopenings 94 which are slightly larger than the finished, routed chipstack. With slight pressure being applied to the stacked panels andsheets, the space between the panels and sheets is easily maintained,thus eliminating the necessity to remove the spacer sheets 92 subsequentto the reflow of the solder. As indicated above, the paper spacer sheets92 would not interfere with the routing process, and would be removedwith the rest of the debris.

[0049] The present assembly method has high volume potential, with theuse of the flux/underfill material providing localized encapsulation ofthe conductive contacts 82 of the integrated circuit chips 70 andeliminating the need for a cleaning cycle as discussed above. Those ofordinary skill in the art will recognize that a transposer panel 86 neednot necessarily be included in the assembly process, since the lowermostbase layer 12 in any chip stack may be used as a transposer board tofacilitate the mounting or electrical connection of the chip stack to aPCB. In the completed chip stack, the solder joints between each of theintegrated circuit chips 70 and the corresponding base layer 12 areprotected by the flux/underfill material.

[0050] Additional modifications and improvements of the presentinvention may also be apparent to those of ordinary skill in the art.Thus, the particular combination of parts and steps described andillustrated herein is intended to represent only one embodiment of thepresent invention, and is not intended to serve as limitations ofalternative devices and methods within the spirit and scope of theinvention.

1. A chip stack comprising: at least two base layers, each of the baselayers comprising: a base substrate; and a first conductive patterndisposed on the base substrate; a least one interconnect frame having asecond conductive pattern disposed thereon, the interconnect frame beingdisposed between the base layers, with the second conductive patternbeing electrically connected to the first conductive pattern of each ofthe base layers; and at least two integrated circuit chips electricallyconnected to respective ones of the first conductive patterns, one ofthe integrated circuit chips being at least partially circumvented bythe interconnect frame and at least partially covered by one of the baselayers.
 2. A chip stack of claim 1 further comprising: a transposerlayer comprising: a transposer substrate; and a third conductive patterndisposed on the transposer substrate; the first conductive pattern ofone of the base layers being electrically connected to the thirdconductive pattern.
 3. The chip stack of claim 2 wherein: the basesubstrate defines opposed top and bottom surfaces; and the firstconductive pattern comprises: a first set of base pads disposed on thetop surface of the base substrate; a second set of base pads disposed onthe top surface of the base substrate and electrically connected torespective ones of the base pads of the first set; and a third set ofbase pads disposed on the bottom surface of the base substrate andelectrically connected to respective ones of the base pads of the secondset; the integrated circuit chips being disposed upon respective ones ofthe top surfaces of the base substrates and electrically connected to atleast some of the base pads of respective ones of the first sets, withthe base pads of the second set of one of the base layers beingelectrically connected to the second conductive pattern, and the basepads of the third set of one of the base layers being electricallyconnected to the second conductive pattern.
 4. The chip stack of claim 3wherein: the interconnect frame defines opposed top and bottom surfaces;and the second conductive pattern comprises: a first set of frame padsdisposed on the top surface of the interconnect frame; and a second setof frame pads disposed on the bottom surface of the interconnect frameand electrically connected to respective ones of the frame pads of thefirst set; the interconnect frame being disposed between the base layerssuch that the frame pads of the second set are electrically connected torespective ones of the base pads of the second set of one of the baselayers, and the frame pads of the first set are electrically connectedto respective ones of the base pads of the third set of one of the baselayers.
 5. The chip stack of claim 4 wherein: the transposer substratedefines opposed top and bottom surfaces; and the third conductivepattern comprises: a first set of transposer pads disposed on the topsurface of the transposer substrate; and a second set of transposer padsdisposed on the bottom surface of the transposer substrate andelectrically connected to respective ones of the transposer pads of thefirst set; the base pads of the third set of one of the base layersbeing electrically connected to respective ones of the transposer padsof the first set.
 6. The chip stack of claim 5 wherein the transposerpads of the first set, the frame pads of the first and second sets, andthe base pads of the second and third sets are arranged in identicalpatterns.
 7. The chip stack of claim 6 wherein: the transposer and basesubstrates each have a generally rectangular configuration definingopposed pairs of longitudinal and lateral peripheral edge segments; theinterconnect frame has a generally rectangular configuration definingopposed pairs of longitudinal and lateral side sections; the transposerpads of the first set extend along the longitudinal and lateralperipheral edge segments of the transposer substrate; the first andsecond sets of frame pads extend along the longitudinal and lateral sidesections of the interconnect frame; and the second and third sets ofbase pads extend along the longitudinal and lateral peripheral edgesegments of the base substrate.
 8. The chip stack of claim 6 whereineach of the transposer pads of the second set has a generally sphericalconfiguration.
 9. The chip stack of claim 6 wherein each of thetransposer pads of the first set and each of the frame pads of the firstand second sets has a generally semi-spherical configuration.
 10. Thechip stack of claim 6 wherein: each of the frame pads of the first setis electrically connected to a respective one of the frame pads of thesecond set via a frame feed-through hole; and each of the base pads ofthe second set is electrically connected to a respective one of the basepads of the third set via a base feed-through hole.
 11. The chip stackof claim 10 wherein each of the frame and base feed-through holes isplugged with a conductive material.
 12. The chip stack of claim 11wherein the conductive material is selected from the group consistingof: nickel; gold; tin; silver epoxy; and combinations thereof.
 13. Thechip stack of claim 6 wherein the integrated circuit chips eachcomprise: a body having opposed, generally planar top and bottomsurfaces; and a plurality of conductive contacts disposed on the bottomsurface of the body; the conductive contacts of each of the integratedcircuit chips being electrically connected to respective ones of thebase pads of the first set of a respective one of the first conductivepatterns.
 14. The chip stack of claim 13 wherein the transposer pads ofthe second set, the base pads of the first set, and the conductivecontacts are arranged in identical patterns.
 15. The chip stack of claim13 further comprising a layer of flux/underfill disposed between thebottom surface of the body of each of the integrated circuit chips andrespective ones of the top surfaces of the base substrates.
 16. The chipstack of claim 13 wherein the body of each of the integrated circuitchips and the interconnect frame are sized relative to each other suchthat the top surface of the body of the integrated circuit chip at leastpartially circumvented by the interconnect frame does not protrudebeyond the top surface thereof.
 17. The chip stack of claim 13 whereinthe integrated circuit chips are each selected from the group consistingof: a BGA device; a fine pitch BGA device; a CSP device; and a flip chipdevice.
 18. The chip stack of claim 2 wherein the transposer and basesubstrates are each fabricated from a polyamide.
 19. The chip stack ofclaim 1 further comprising: a second interconnect frame, the secondconductive pattern of which is electrically connected to the firstconductive pattern of one of the base layers such that the secondinterconnect frame at least partially circumvents one the integratedcircuit chips; a third base layer, the first conductive pattern of whichis electrically connected to the second conductive pattern of the secondinterconnect frame such that the third base layer at least partiallycovers one of the integrated circuit chips; and a third integratedcircuit chip electrically connected to the first conductive pattern ofthe third base layer.
 20. The chip stack of claim 19 further comprising:a multiplicity of additional interconnect frames, base layers, andintegrated circuit chips; the second conductive pattern of each of theinterconnect frames being electrically connected to the first conductivepatterns of any adjacent pair of base layers, with each of theintegrated circuit chips being electrically connected to the firstconductive pattern of a respective one of the base layers.
 21. A methodof assembling a chip stack, comprising the steps of: (a) electricallyconnecting an integrated circuit chip to a first conductive pattern of abase layer; (b) electrically connecting a second conductive pattern ofan interconnect frame to the first conductive pattern such theinterconnect frame at least partially circumvents the integrated circuitchip; (c) electrically connecting another integrated circuit chip to thefirst conductive pattern of another base layer; and (d) electricallyconnecting the first conductive pattern of one of the base layers to thesecond conductive pattern of the interconnect frame such that one of theintegrated circuit chips is disposed between the base layers.
 22. Themethod of claim 21 further comprising the step of: (e) electricallyconnecting the first conductive pattern of one of the base layers to athird conductive pattern of a transposer layer.
 23. The method of claim21 wherein steps (a) and (c) each comprise applying a layer offlux/underfill to each of the base layers over portions of the firstconductive patterns prior to the electrical connection of respectiveones of the integrated circuit chips thereto.
 24. The method of claim 22wherein steps (a)-(e) are accomplished via soldering.
 25. A method ofassembling a chip stack, comprising the steps of: (a) providing atransposer panel which has opposed surfaces and a plurality ofconductive pads disposed on the opposed surfaces thereof; (b) providingat least two base panels which each have opposed surfaces and aplurality of conductive pads disposed on the opposed surfaces thereof;(c) providing at least one frame panel which has opposed surfaces and aplurality of conductive pads disposed on the opposed surfaces thereof;(d) providing a plurality of integrated circuit chips which each haveopposed sides and a plurality of conductive contacts disposed on one ofthe sides thereof; (e) placing integrated circuit chips upon each of thebase panels such that the conductive contacts of each of the integratedcircuit chips are disposed on at least some of the conductive pads ofrespective ones of the base panels; (f) stacking one of the base panelsupon the transposer panel such that at least some of the conductive padsof the base panel are disposed on at least some of the conductive padsof the transposer panel; (g) stacking the frame panel upon the basepanel such that at least some of the conductive pads of the frame panelare disposed on at least some of the conductive pads of the base panel;and (h) stacking another base panel upon the frame panel such that atleast some of the conductive pads of the base panel are disposed on atleast some of the conductive pads of the frame panel.
 26. The method ofclaim 25 wherein steps (g) and (h) are repeated at least once subsequentto step (h).
 27. The method of claim 25 further comprising the step of:(i) bonding the conductive contacts of the integrated circuit chips toat least some of the conductive pads of the base panel upon which theintegrated circuit chips are positioned, bonding at least some of theconductive pads of one of the base panels to at least some of theconductive pads of the transposer panel, and bonding at least some ofthe conductive pads of the frame panel to at least some of theconductive pads of each of the base panels.
 28. The method of claim 25wherein at least three spacer sheets are also provided which each haveopposed surfaces and a plurality of openings disposed therein, and: step(f) comprises stacking one of the spacer sheets upon the transposerpanel and stacking the base panel upon the spacer sheet such that theconductive pads of the transposer and base panels are aligned withrespective ones of the openings; step (g) comprises stacking anotherspacer sheet upon the base panel and stacking the frame panel upon thespacer sheet such that the conductive pads of the base and frame panelsare aligned with respective ones of the openings; and step (h) comprisesstacking another spacer sheet upon the frame panel and stacking the basepanel upon the spacer sheet such that the conductive pads of the frameand base panels are aligned with respective ones of the openings.